1. Field of the Invention
The present invention relates to memory devices and, more particularly, to methods of treating over-erase conditions of non-volatile memory devices.
2. Description of Related Art
Semiconductor devices typically include multiple individual components formed on or within a substrate. One such component is a memory device, which is used to store electronic data such as computer programs executed by an electronic processor and logical data operated on by the processor. Memory devices that do not require ambient power to store electronic data are commonly referred to as non-volatile memory devices. The read-only memory (ROM) is a non-volatile memory device commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices such as cellular phones.
ROM devices are conventionally arranged into a plurality of memory cell arrays. Each memory cell includes a transistor, which typically comprises a metal-oxide-semiconductor field effect transistor (MOSFET) that is juxtaposed between two intersecting bit lines and a word line. Data bit values or codes held by these memory cell transistors are permanently stored (until deliberate erase) in the physical or electrical properties of the individual memory cells. Generally speaking, a consequence of the non-volatile nature of a ROM is that data stored in the memory device can only be read.
Programmable non-volatile memory is a specific form of non-volatile memory in which bits of logical data can not only be read but can also be written (e.g., programmed) into memory cells. In general, a grouping of memory cells can be termed a word, a grouping of words can be termed a page, and a grouping of pages can be termed a sector. Data may be accessed for reading and programming (i.e., writing) by word or page, while an entire sector is commonly accessed for erasing.
Three commonly-known types of these nonvolatile ROMs are erasable programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROM), and flash EEPROMs, which are commonly referred to as flash memories. These all can be written to by one of two ways. The first is by channel hot electron (CHE) injection. This is accomplished by injecting electrons to modify the voltage at a transistor's floating gate. The second method of writing employs a field emission mechanism known as Fowler-Nordheim (F-N) tunneling. Fowler-Nordheim tunneling is the process whereby electrons tunnel through a barrier in the presence of a high electric field. This quantum mechanical tunneling process is an important mechanism for thin barriers such as those in metal- or oxide-semiconductor junctions on highly-doped semiconductors. F-N tunneling is achieved by applying a field across the insulating barrier to make it transparent for electrons to pass through. Erasing the above memories can be performed for example by either F-N tunneling or by exposing them to ultraviolet light. EPROMs can use CHE for writing and ultraviolet light for erasing. EEPROMs can use F-N tunneling for both writing and erasing. Flash memories can use CHE for writing and F-N tunneling for erasing.
A conventional floating gate-based flash memory device (e.g., a floating gate-based EEPROM) includes a transistor characterized by a programmable threshold voltage (Vt). The transistor's threshold voltage can be set, or programmed, to a desired value along an analog scale between the maximum and minimum threshold voltage limits that are determined based on the design parameters of the transistor. The transistor typically comprises a stacked gate structure on a semiconductor substrate. The stacked gate structure includes a relatively thin tunnel oxide (i.e., silicon dioxide) that overlies the substrate. It also includes a doped polysilicon floating gate that overlies the tunnel oxide and an interpoly dielectric that overlies the floating gate. Lastly, a doped polysilicon control gate overlies the interpoly dielectric. The transistor also comprises source and drain regions that are self-aligned to the sidewalls of the stacked gate structure.
In general, a floating gate-based flash memory device can be programmed by inducing electron injection from either the source region or the drain region, depending upon the applied voltage bias, to the floating gate. Electrons pass through the tunnel oxide to the floating gate by a mechanism known as Fowler-Nordheim (F-N) tunneling. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of the associated field effect transistor (FET) and inhibits current flow through the channel region during a subsequent “read” mode. The act of discharging the floating gate, (i.e., the erase function), can be carried out by inducing the electrons stored in the floating gate to move to the source region. There are numerous ways to move electrons to or from the floating gate. For example, the electrons can be electrically drawn or, alternatively, they can be drawn using ultraviolet radiation.
A relatively recent development in non-volatile memory has been the advent of localized trapped charge devices. While these devices are commonly referred to as nitride read-only memory (NROM) devices, the acronym “NROM” is part of a combination trademark of Saifim Semiconductors Ltd. (Netanya, Israel). NROM devices offer a number of advantages over the 30 year old currently dominant floating gate devices such as EPROM, Flash, and EEPROM, which store charge in a conductive floating gate.
Each memory device of a localized trapped charge array is typically an n-channel MOS (nMOS) transistor with an oxide-nitride-oxide (ONO) dielectric structure forming the gate dielectric. Data is stored in two separate locations adjacent to the source and drain terminals of the nMOS transistor, allowing 2 bits of data to be stored in the nMOS transistor structure.
A localized trapped charge memory device (e.g., NROM-based device) may be typically programmed by channel hot electron (CHE) injection through bottom oxide layers of the ONO dielectric structures. That is, by inducing electron injection from the drain region to the charge trapping layer. Electrons pass through the tunnel oxide to the charge trapping layer by the mechanism of F-N tunneling mentioned earlier. During programming, electrical charge is trapped in the charge trapping layer. Since this charge trapping layer comprises a non-conductive or low conductivity material (e.g., silicon nitride), as well as because of the relatively low lateral electric field in the charge trapping layer, the individual electrical charges do not migrate within the charge trapping layer.
The localized trapped charge memory device may be erased by tunneling enhanced hot hole (TEHH) injection. In the TEHH injection mechanism, holes are generated by band-to-band tunneling under the ONO dielectric structure in the junction. The kinetic energy of the holes is increased due to a lateral electric field, allowing some holes to be injected into the ONO dielectric structure, assisted by a vertical electric field. Once in the ONO dielectric structure, the holes combine with stored electrons. An erase cycle may be performed with a positive voltage scheme, with a positive voltage bias from the drain to the source, and with the gate being grounded. Alternatively, a positive voltage may be applied to the drain, and a negative voltage to the gate. The NROM-based device operates as a localized charge storage device, in which the trapped charge remains only at the injection point. Thus, NROM-based devices can be less susceptible to single bit failures commonly experienced by some floating gate technologies, and the occurrence of these types of failures may be reduced. Scaling reduction (i.e., reduction in size) may allow for further minimization of overall device size and increased device density without degradation in performance.
A troublesome problem associated with localized trapped charge memory devices can be that of “over-erase.” Generally, over-erase can occur for example when a cell's or bit's threshold voltage is lowered during an erase operation to the point where it cannot be sufficiently turned off when de-selected following the erase operation. In the context of an NROM-based memory device, an over-erase condition can result from the removal of too many electrons from the charge trapping layer of the NROM-based memory device. For instance, an over-erase condition can occur in an NROM-based memory device when more electrons are removed from a charge trapping layer than were placed there by a previous cell protocol.
It would thus be advantageous to have a method of erase applicable to a non-volatile memory device, such as an NROM-based device, in which an over-erase condition can be attenuated or altogether eliminated.